Hello,

More precision, read again about more of my philosophy about DDR5 and
the next Sapphire Rapids CPU of Intel..

I am a white arab from Morocco, and i think i am smart since i have also
invented many scalable algorithms and algorithms..

I will explain something very important:

I invite you to read the following about the next Sapphire Rapids CPU of
Intel here:

Intel Provides Details About Sapphire Rapids CPU and Ponte Vecchio GPU

https://www.hpcwire.com/off-the-wire/intel-unveils-details-about-sapphire-rapids-cpu-ponte-vecchio-gpu-ipu/

So notice carefully that it says the following:

"The processor is built to drive industry technology transitions with
advanced memory and next generation I/O, including PCIe 5.0, CXL 1.1,
DDR5 and HBM technologies."

And notice that it says the same here:

https://en.wikipedia.org/wiki/Sapphire_Rapids

So the next Sapphire Rapids CPU of Intel will support DDR5 and HBM
technologies for the memory subsystem, but i will say that CPUs like the
kind of CPUs for computer servers have implemented ECC in their caches
for at least a decade or so, and DDR5 memory subsystem implementations
are useful for creating large capacities with modest bandwidth compared
to HBM, and HBM, on the other hand, offers large bandwidth with low
capacity, but i think that the problem with the next Sapphire Rapids CPU
of Intel is that DDR5 has a problem that it is not fully ECC, read here
to notice it:

"On-die ECC: The presence of on-die ECC on DDR5 memory has been the
subject of many discussions and a lot of confusion among consumers and
the press alike. Unlike standard ECC, on-die ECC primarily aims to
improve yields at advanced process nodes, thereby allowing for cheaper
DRAM chips. On-die ECC only detects errors if they take place within a
cell or row during refreshes. When the data is moved from the cell to
the cache or the CPU, if there’s a bit-flip or data corruption, it won’t
be corrected by on-die ECC. Standard ECC corrects data corruption within
the cell and as it is moved to another device or an ECC-supported SoC."

Read more here to notice it:

https://www.hardwaretimes.com/ddr5-vs-ddr4-ram-quad-channel-and-on-die-ecc-explained/

Thank you,
Amine Moulay Ramdane.