Hello,

More of my philosophy about the good technicality and the deeper understanding of the StopWatch and and more about x86 and ARM processors and about solar cells and about AES 256 encryption and TSMC and about China and about the Transformers and about Toyota and about China and about objective truth and about the objective and about the paper about the multiple universes and about quantum world and about consciousness and about mathematics and about the universe and about mathematical probability and about the positive behavior and about the positive mindset and about patience and about the positive energy and about the "packaging" or "presentation" and about the ideal and about the being idealistic and more of my thoughts..

I am a white arab from Morocco, and i think i am smart since i have also
invented many scalable algorithms and algorithms..

So i have just updated my new StopWatch, so the first problem is:

- Instruction reordering: The rdtsc instruction itself is not a serializing instruction, which means that it does not necessarily prevent instruction reordering. In certain cases, the CPU may reorder instructions, leading to inaccuracies in timing measurements.

So i have just used memory barriers so that to solve the above problem.

And here is the second problem:

- CPU frequency scaling: Modern CPUs often have dynamic frequency scaling, where the CPU frequency can change based on factors such as power management and workload. This can result in variations in the time measurement based on the CPU's operating frequency.

So you have to disable CPU frequency scaling in the bios so that to solve the
above problem , and after that make your timing with my StopWatch.

And for the following third problem:

- Multicore/Threaded environments: If your system has multiple cores or threads, using rdtsc may not provide synchronized timing across different cores or threads. This can lead to inconsistent and unreliable timing measurements.

You can set the CPU affinity so that to solve the third problem.

So i will document more my StopWatch so that to learn you how to use it,
so stay tuned !
And now i have just updated my new StopWatch with the necessary memory barriers, and now you can be confident with my new updated StopWatch.

So now my new updated StopWatch uses memory barriers correctly, and it avoids the overflow problem of the Time Stamp Counter (TSC) , and it supports microseconds and nanoseconds and CPU clocks timing, and i have just made it support both x86 32 bit and x64 64 bit CPUs and it supports both Delphi and Freepascal compilers and it works in both Windows and Linux, so what is good about my new StopWatch is that it shows how you implement it from the low level layers in assembler etc., so i invite you to look at the new updated version of my source code that you can download from my website here:

https://sites.google.com/site/scalable68/a-portable-timer-for-delphi-and-freepascal

Other than that read my below previous thoughts so that to understand my views:

So now we have to attain a "deep" understanding of the StopWatch,
so i think i am highly smart since I have passed two certified IQ tests and i have scored above 115 IQ, and i mean that it is "above" 115 IQ, so as you are noticing that i am, with my fluid intelligence, understanding deeply the StopWatch, so i have just discovered that the following StopWatch: https://www.davdata.nl/math/timer.html , from the following engineer from Amsterdam: https://www.davdata.nl/math/about.html , is not working correctly: since he is calling the function GetTickCount() in the constructor, but there is a problem and a bug, since when the tick count value in milliseconds returned by GetTickCount() reaches its maximum value in that is high(dword) , it will wrap around to zero and start counting up again. This is because the tick count is typically stored in a fixed-size data type that has a maximum value, so it is why his way of timing in milliseconds in the constructor that he is using is not working, since it is not safe, so even if this StopWatch of this engineer from Amsterdam does effectively avoid the overflow problem of the Time Stamp Counter (TSC), since he is using an int64 in 32 bit x86 architecture in the Intel assembler function of getCPUticks() that i am understanding, and this int64 can, from my calculations, go up to 29318.9829 years , so i think his StopWatch is not working for the reason i am giving just above, and second problem is the accuracy of the timing obtained from the code he provided using rdtsc instruction in assembler is dependent on various factors, including the hardware and software environment. However, it's important to note that directly using rdtsc for timing purposes may not provide the desired accuracy due to several reasons:

- CPU frequency scaling: Modern CPUs often have dynamic frequency scaling, where the CPU frequency can change based on factors such as power management and workload. This can result in variations in the time measurement based on the CPU's operating frequency.

- Instruction reordering: The rdtsc instruction itself is not a serializing instruction, which means that it does not necessarily prevent instruction reordering. In certain cases, the CPU may reorder instructions, leading to inaccuracies in timing measurements.

- Multicore/Threaded environments: If your system has multiple cores or threads, using rdtsc may not provide synchronized timing across different cores or threads. This can lead to inconsistent and unreliable timing measurements.

So I have just thought more and i think i will not support ARM in my new StopWatch, since ARM processors don't support like a Time Stamp Counter (TSC) in x86 processors that is compatible with previous 32 bit and 64 bit CPUs , so ARM has many important weaknesses , so the first important weakness is the following:

There is no single generic method that can be universally applied to all Arm processors for measuring time in CPU clocks. The available timing mechanisms and registers can vary significantly across different Arm processor architectures, models, and specific implementations.

In general, Arm processors provide various timer peripherals or system registers that can be used for timing purposes. However, the specific names, addresses, and functionalities of these timers can differ between different processors.

To accurately measure time in CPU clocks on a specific Arm processor, you would need to consult the processor's documentation or technical reference manual. These resources provide detailed information about the available timers, their registers, and how to access and utilize them for timing purposes.

It's worth noting that some Arm processors may provide performance monitoring counters (PMCs) that can be used for fine-grained timing measurements. However, the availability and usage of PMCs can also vary depending on the specific processor model.

Therefore, to achieve accurate and reliable timing measurements in CPU clocks on a particular Arm processor, it's crucial to refer to the documentation and resources provided by the processor manufacturer for the specific processor model you are targeting.

And the other weaknesses of ARM processors are the following:

I have just looked at the following articles about Rosetta 2 and the benchmarks of Apple Silicon M1 Emulating x86:

https://www.computerworld.com/article/3597949/everything-you-need-to-know-about-rosetta-2-on-apple-silicon-macs.html

and read also here:

https://www.macrumors.com/2020/11/15/m1-chip-emulating-x86-benchmark/

But i think that the problem with Apple Silicon M1 and the next Apple SiliconM2 is that Rosetta 2 only lets you run x86–64 macOS apps. That would be apps that were built for macOS (not Windows) and aren't 32-bit. The macOS restriction eliminates huge numbers of Windows apps, and 64-bit restriction eliminates even more.

Also read the following:

Apple says new M2 chip won’t beat Intel’s finest

Read more here:

https://www.pcworld.com/article/782139/apple-m2-chip-wont-beat-intels-finest.html

And here is what i am saying on my following thoughts about technology about Arm Vs. X86:

More of my philosophy about the Apple Silicon and about Arm Vs. X86 and more of my thoughts..

I invite you to read carefully the following interesting article so
that to understand more:

Overhyped Apple Silicon: Arm Vs. X86 Is Irrelevant

https://seekingalpha.com/article/4447703-overhyped-apple-silicon-arm-vs-x86-is-irrelevant

More of my philosophy about code compression of RISC-V and ARM and more of my thoughts..

I think i am highly smart, and i have just read the following paper
that says that RISC-V Compressed programs are 25% smaller than RISC-V programs, fetch 25% fewer instruction bits than RISC-V programs, and incur fewer instruction cache misses. Its code size is competitive with other compressed RISCs. RVC is expected to improve the performance and energy per operation of RISC-V.

Read more here to notice it:

https://people.eecs.berkeley.edu/~krste/papers/waterman-ms.pdf

So i think RVC has the same compression as ARM Thumb-2, so i think
that i was correct in my previous thoughts , read them below,
so i think we have now to look if the x86 or x64 are still more cache friendly even with Thumb-2 compression or RVC.

More of my philosophy of who will be the winner, x86 or x64 or ARM and more of my thoughts..

I think i am highly smart, and i think that since x86 or x64 has complex instructions and ARM has simple instructions, so i think that x86 or x64 is more cache friendly, but ARM has wanted to solve the problem by compressing the code by using Thumb-2 that compresses the code, so i think Thumb-2 compresses the size of the code by around 25%, so i think
we have to look if the x86 or x64 are still more cache friendly even with Thumb-2 compression, and i think that x86 or x64 will still optimize more the power or energy efficiency, so i think that there remains that since x86 or x64 has other big advantages, like the advantage that i am talking about below, so i think the x86 or x64 will be still successful big players in the future, so i think it will be the "tendency". So i think that x86 and x64 will be good for a long time to make money in business, and they will be good for business for USA that make the AMD or Intel CPUs.