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It's hard to tune heavily tuned code. :-) -- Larry Wall in <199801141725.JAA07555@wall.org>


devel / comp.lang.verilog

1
SubjectRepliesLast Message
o Open source 8b10b encoder/decoder, verilog

By: Nrusimhadri Vyshnavi on Tue, 5 Dec 2023

0

4 Months 19 Days ago

By: Nrusimhadri Vyshnavi

o SPI Slave clock

By: khan on Wed, 11 Oct 2023

1

5 Months ago

By: littlewing

o Comp.lang.verilog RIP

By: gnuarm.del...@gmail. on Sat, 21 Oct 2023

0

6 Months 3 Days ago

By: gnuarm.del...@gmail.

o Clocks not toggling in gate level simulation

By: shriya ate on Mon, 25 Sep 2023

0

6 Months 30 Days ago

By: shriya ate

o How to implant the artificial neural network model to Verilog-A

By: 林清流 on Wed, 9 Aug 2023

0

8 Months 15 Days ago

By: 林清流

o system verilog

By: Shivangi Sharma on Thu, 29 Jun 2023

0

9 Months 26 Days ago

By: Shivangi Sharma

o Use of Both Posedge Clk and Negedge Clock

By: e liu on Sat, 24 Jun 2023

1

10 Months ago

By: gnuarm.del...@gmail.

o How can I stop the simualtion at stop bit for i2c master verilog code?

By: Qazi Zabeer on Mon, 5 Jun 2023

1

10 Months 19 Days ago

By: Charlie

1

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